A serializer/deserializer (SERDES) may be used as a transceiver within a network environment. The transmitter section of a SERDES accepts a parallel data word (which is typically 8-bit/10-bit encoded) and provides multiplexing into a single data stream having a transmission rate that is ten times the parallel rate. Conventionally, the outgoing parallel data is latched into the input register of the transmitter on the rising edge of a reference clock, but is serialized and transmitted at a speed of approximately ten times the reference clock. The high speed serial output may be connected to a copper cable for electrical transmission or may be converted to optical signals for transmission via a fiber optic cable.
The receive section of a SERDES recovers original 10-bit wide parallel data. That is, the received section is a deserializer. This section may employ a phase-locked loop (PLL) to determine the clocking for the recovered data. Clock recovery may be achieved by locking onto the frequency of the reference clock and by phase locking onto the incoming data stream.
Originally, the serializer was fabricated as one integrated circuit (IC) chip, while the deserializer was formed as a separate IC chip. In a first round of integration, the serialization function block and deserialization function block were integrated into a single IC chip. The motivations for the integration included reducing the total chip count and reducing the required board real estate. The same motivations applied to a second round of integration in which multiple SERDESs were incorporated into a single IC chip. As a third round of integration, application-specific circuitry may be embedded with the multiple SERDESs. For example, the circuitry of a switch logic chip may be integrated into the SERDES chip, thereby removing the necessity of providing parallel data lines which connect a switch logic chip to a SERDES chip. In addition to preserving board real estate, significant reductions in required power are realized at this level of integration.
Potential concerns that are raised by the integration of SERDES-related circuitry into a single IC chip include determining a testing approach that is sufficiently thorough. Preferably, each SERDES within a highly integrated chip is individually tested and the different components of each SERDES are tested at their different specific speeds to ensure proper functionality. During testing, the parallel data at the serializer input (i.e., Tx input) is dynamically toggled and the recovered data at the deserializer input (i.e., Rx input) is compared to the transmitted data. The tests are executed over various modes, such as a loop-back mode and a byte-sync enable mode. A functional test at the specific speed ensures that the signal integrity of the output drivers and the subtle behaviors of the PLLs are all tested.
The stimuli and measurements of the data may be provided and performed using an external high-speed IC test system. One test system is referred to as the Bit-Error-Rate Tester (BERT). The BERT generates pseudo-random bit sequence (PRBS) patterns and continuously monitors the received PRBS patterns for errors. A high volume of data is channeled through a SERDES by a BERT, which records any errors in order to determine the bit error rate. Since the parallel signals which interface the embedded SERDESs with the embedded core logic, such as switch core logic, are internal to highly integrated IC chips, the traditional methods of testing are difficult or impossible to apply. Thus, what is needed is a method of testing the SERDES circuitry within a highly integrated IC chip.
Particularly where a SERDES utilizes analog functionality (such as within its PLLs), the SERDES is sensitive to crosstalk and power supply variations. Thus, testing the functionality of a single embedded SERDES channel does not ensure that the SERDES which supports that channel will function properly when all of its channels are active. It follows that proper testing requires all embedded SERDESs to be operating simultaneously.
What is needed is a multiple-SERDES testing capability that can be applied to highly integrated IC chips, with the testing being adapted to simulate a real-time environment of operation.